An embodiment of this disclosure relates to a semiconductor device and a method of operating the same and, more particularly, to the controller of a semiconductor device for controlling page buffers.
A semiconductor device includes a memory cell array for storing data and a plurality of circuits for storing data in the memory cell array or reading data stored in the memory cell array. A page buffer included in the plurality of circuits controls voltages of bit lines, coupled to the memory cell array, in response to page buffer signals generated from the controller.
FIG. 1 is a circuit diagram illustrating a conventional controller and a conventional page buffer.
Referring to FIG. 1, a semiconductor device includes a memory cell array 10, a plurality of page buffers 20, and a controller 40.
The memory cell array 10 includes a plurality of memory blocks. Each of the memory blocks includes a plurality of cell strings each coupled between a bit line BLe or BLo and a common source line CSL. The cell strings are divided into even cell strings STe and odd cell strings STo according to an order of their arrangements. FIG. 1 shows a pair of even and odd cell strings STe and STo included in one of the memory blocks. A bit line coupled to the even cell string STe is called an even bit line BLe, and a bit line coupled to the odd cell string STo is called an odd bit line BLo. The cell strings have the same construction, and thus only the even cell string Ste is described in detail below as an example.
The even cell string STe includes a drain select transistor DST, a plurality of memory cells F0 to Fn, and a source select transistor SST which are coupled in series between the even bit line BLe and the common source line CSL. The gates of the drain select transistors DST included in the cell strings STe and STo are coupled to a drain select line DSL, the gates of the memory cells F0 to Fn included in the cell strings STe and STo are coupled to a plurality of word lines WL0 to WLn, and the gates of the source select transistors SST included in the cell strings STe and STo are coupled to a source select line SSL.
The page buffer 20 includes a bit line selection circuit 30 for selecting one of the bit lines BLe and BLo, a sense circuit 22 for transferring the potential of a selected bit line to a sense node SO in a read operation, a precharge circuit 21 for precharging the sense node SO, a first latch 25 and a second latch 26 for storing data, a first transfer circuit 23 for transferring data, stored in the first latch 25, to the sense node SO, a second transfer circuit 24 for transferring data, stored in the second latch 26, to the sense node SO, a first set/reset circuit 27 for setting up or resetting the first latch 25, a second set/reset circuit 28 for setting up or resetting the second latch 26, and a discharge circuit 29 for discharging a common node CON.
The bit line selection circuit 30 includes a bit line precharge circuit 31 for precharging the even bit line BLe or the odd bit line BLo in a program operation and a selection circuit 32 for selecting the even bit line BLe or the odd bit line BLo.
The bit line precharge circuit 31 includes a first switch N01 for precharging the even bit line BLe in response to an even precharge signal DISE and a second switch N02 for precharging the odd bit line BLO in response to an odd precharge signal DISO. The first switch N01 is formed of an NMOS transistor coupled between the even bit line BLe and a terminal for supplying virtual voltage VIRPWR. The second switch N02 is formed of an NMOS transistor coupled between the odd bit line BLe and the terminal for supplying the virtual voltage VIRPWR.
The selection circuit 32 includes a third switch N03 for selecting the even bit line BLe in response to an even selection signal BSLE and a fourth switch N04 for selecting the odd bit line BLo in response to an odd selection signal BSLO. Each of the third switch N03 and the fourth switch N04 is formed of an NMOS transistor.
The sense circuit 22 includes a fifth switch N05 for coupling a selected bit line and the sense node SO in response to a sense signal PBSENSE. The fifth switch N05 is formed of an NMOS transistor.
The precharge circuit 21 includes a sixth switch N06 for coupling a terminal for a power supply voltage VDD and the sense node SO in response to a precharge signal PRECHb and precharging the sense node SO. The sixth switch N06 is formed of a PMOS transistor.
The first latch 25 includes first and second inverters I1 and I2. The output terminal of the first inverter I1 and the input terminal of the second inverter I2 are coupled to a node QA, and the output terminal of the second inverter I2 and the input terminal of the first inverter I1 are coupled to each other.
The second latch 26 includes third and fourth inverters I3 and I4. The output terminal of the third inverter I3 and the input terminal of the fourth inverter I4 are coupled to a node QB, and the output terminal of the fourth inverter I4 and the input terminal of the third inverter I3 are coupled to each other. Although only the two latches 25 and 26 are illustrated as being included in the page buffer 20 of FIG. 1, one latch or three or more latches may be included in the page buffer 20 according to a semiconductor device.
The first transfer circuit 23 includes an eighth switch N08 for coupling the output terminal of the first inverter I1 and the sense node SO in response to a first transfer signal TRANM. The eighth switch N08 is formed of an NMOS transistor.
The second transfer circuit 24 includes a tenth switch N10 for coupling the output terminal of the third inverter I3 and the sense node SO in response to a second transfer signal TRANC. The tenth switch N10 is formed of an NMOS transistor.
The first set/reset circuit 27 includes an 11th switch N11 for resetting the first latch 25 by coupling the output terminal of the second inverter I2 and the common node CON in response to a first reset signal RESET_A and a 12th switch N12 for setting up the first latch 25 by coupling the input terminal of the second inverter I2 and the common node CON in response to a first set signal SET_A. Each of the 11th and the 12th switches N11 and N12 is formed of an NMOS transistor.
The second set/reset circuit 28 includes a 13th switch N13 for resetting the first latch 26 by coupling the output terminal of the fourth inverter I4 and the common node CON in response to a second reset signal RESET_B and a 14th switch N14 for setting up the first latch 26 by coupling the input terminal of the fourth inverter I4 and the common node CON in response to a second set signal SET_B. Each of the 13th and the 14th switches N13 and N14 is formed of an NMOS transistor.
The discharge circuit 29 includes a 15th switch N15 for discharging the common node CON by coupling the common node CON and a ground terminal Vss in response to voltage of a sense node SO. The 15th switch N15 is formed of an NMOS transistor.
The controller 40 includes a plurality of circuits for controlling circuits included in the semiconductor device. FIG. 1 shows a page buffer control circuit (50 and 60) from among the plurality of circuits. The page buffer control circuit (50 and 60) includes a high voltage generation unit 50 for generating high voltages and a voltage divider unit 60 for converting the high voltages of the high voltage generation unit 50 in the form of page buffer control signals PB SIGNALS having various levels and outputting the page buffer control signals PB SIGNALS. The high voltage generation unit 50 includes first to kth high voltage generators HV1 to HVk for generating the respective high voltages in response to first to kth control signals CON1 to CONk. The voltage divider unit 60 includes first to kth voltage dividers DIV1 to DIVk for outputting the high voltages in the form of the respective page buffer control signals PB SIGNALS having various levels. According to an example, the reason why a plurality of the first to kth high voltage generators HV1 to HVk is used as high voltage sources for the page buffer control signals PB SIGNALS is to make the page buffer control signals PB SIGNALS rapidly reach a target level. For example, the first voltage divider DIV1 may receive the high voltage from the first high voltage generator HV1 and output the even precharge signal DISE for turning on the first switch N01. The second voltage divider DIV2 may receive the high voltage from the second high voltage generator HV2 and output the odd precharge signal DISO. Likewise, the voltage dividers DIV1 to DIVk may receive the respective high voltages from the high voltage generators HV1 to HVk and output the respective page buffer control signals PB SIGNALS for turning on or off the switches included in the page buffer 20.
If the plurality of high voltage generators HV1 to HVk are used as the high voltage sources for the page buffer control signals PB SIGNALS, however, the operating speed of the page buffer 20 may be increased, but the amount of current consumed by the plurality of high voltage generators HV1 to HVk is increased because the plurality of high voltage generators are driven. According to an example, capacitance between the even and odd bit lines (that is, parasitic capacitive coupling between the even and odd bit lines) is greatly increased because the number of program data ‘0’ is larger in the early stage of a program operation than in the latter part of the program operation. For this reason, in raising the potentials of unselected bit lines up to a level equivalent to a program inhibition voltage Vcc, a peak current rises. At this time, the amount of current may suddenly rise.